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CPC7220
Low Charge Injection 8-Channel High Voltage Analog Switch
Features
* Processed with BCDMOS on SOI (Silicon On Insulator) * DC to 10MHz analog signal frequency * Surface mount package available * Low quiescent power dissipation (< 1A typical) * Output on-resistance typically 20 * TTL I/O's for 3.3V interface * Adjustable high voltage supplies
Description
The CPC7220 is a low charge injection 8-channel high-voltage analog switch integrated circuit (IC) for use in applications requiring high voltage switching. Control of the high voltage switching is via low voltage TTL logic level compatible inputs for direct connectivity to the system controller.
Applications
* Ultrasound imaging * Printers * Industrial controls and measurement
Block Diagram
SHIFT REGISTER CLK DIN SR0 L0 D LE CL L1 D LE CL L2 D LE CL L3 D LE CL L4 D LE CL L5 D LE CL L6 D LE CL L7 D LE CL LS0 LATCHES LEVEL SHIFTERS SWITCHES
SR1
SR2
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LS1 LS2 LS3 LS4 LS5 LS6 LS7 VPP VNN
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SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
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Because the CPC7220 is capable of switching high load voltages and has a flexible load voltage range, e.g. VPP/VNN : +40V/-160V or +100V/-100V, it is well suited for many medical and industrial applications such as medical ultrasound imaging, printers, and industrial measurement equipment. Construction of the high voltage switches using Clare's reliable BCDMOS process technology on SOI (Silicon On Insulator) allow the switches to be organized as solid state switches with direct gate drive.
Ordering Information
Part Number CPC7220W CPC7220WTR CPC7220K CPC7220KTR Description 28-Lead PLCC in Tubes (37/Tube) 28-Lead PLCC Tape & Reel (500/Reel) 48-Lead LQFP in Trays (250/Tray) 48-Lead LQFP Tape & Reel (1000/Reel)
SR4
SR5
SR6
SR7 DOUT CL LE
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Switch manipulation is managed by an 8-bit serial to parallel shift register whose outputs are buffered and stored by an 8-bit transparent latch. Level shifters buffer the latch outputs and operate the high voltage switches.
CPC7220
PLCC Package Pinout Pin Descriptions
CPC7220 1 2 3 4 5 6 7 8 10 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 9, 11, 15 Name SW3 SW3 SW2 SW2 SW1 SW1 SW0 SW0 VPP VNN GND VDD DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 N/C Description SW3 output SW3 output SW2 output SW2 output SW1 output SW1 output SW0 output SW0 output Switch positive high voltage supply Switch negative high voltage supply Ground Logic positive voltage supply Serial data input Clock input, positive edge trigger Latch enable, active low Latch clear, active high clears latches and opens switches Serial data output SW7 output SW7 output SW6 output SW6 output SW5 output SW5 output SW4 output SW4 output No Connection
25 26
27
24
23
22
21
20
19 18 17 16 15 14 13 12
28 1 2 3 4 5 6 7 8 9 10 11
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LQFP Package Pinout
48 47 46 45 44 43 42 41 40 39 38 37
Pin Descriptions
CPC7220 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name SW5 N/C SW4 N/C SW4 N/C N/C SW3 N/C SW3 N/C SW2 N/C SW2 N/C SW1 N/C SW1 N/C SW0 N/C SW0 N/C VPP VNN N/C N/C GND VDD N/C N/C N/C DIN CLK LE CL DOUT N/C SW7 N/C SW7 N/C SW6 N/C SW6 N/C SW5 N/C Description SW5 output No Connection SW4 output No Connection SW4 output No Connection No Connection SW3 output No Connection SW3 output No Connection SW2 output No Connection SW2 output No Connection SW1 output No Connection SW1 output No Connection SW0 output No Connection SW0 output No Connection Switch positive high voltage supply Switch negative high voltage supply No Connection No Connection Ground Logic positive voltage supply No Connection No Connection No Connection Serial data input Clock input, positive edge trigger Latch enable, active low Latch clear, active high clears latches and opens switches Serial data output No Connection SW7 output No Connection SW7 output No Connection SW6 output No Connection SW6 output No Connection SW5 output No Connection
13 14 15 16 17 18 19 20 21 22 23 24
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1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
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CPC7220
Absolute Maximum Ratings (@ 25 C)
Parameter VDD logic power supply voltage VPP - VNN supply voltage VPP positive high voltage supply VNN negative high voltage supply Logic input voltages Analog signal range Peak analog signal current/channel Power dissipation Storage Temperature Ratings -0.5 to +6 220 -0.5 to VNN +200 +0.5 to VPP -200 -0.5 to VDD +0.3 VNN to VPP 1 1.2 -60 to +150 Units V V V V V A W C Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied.
Operating Conditions
Parameter Logic power supply voltage 1,3 Positive high voltage supply 1,3 Negative high voltage supply 1,3 Analog signal voltage peak to peak 2 Operating temperature
NOTES:
1 2 3
Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. VSIG must be VNN VSIG VPP or floating during power up/down transition. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1msec.
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Symbol VDD VPP VNN VSIG TA
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Value 4.5V to 6V 40V to VNN + 200V -40V to -160V VNN + 10V to VPP -10V 0C to 70C
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Electrical Characteristcs
DC Characteristics (over recommended operating conditions unless otherwise noted) 0C +25C +70C Parameter Symbol Test Conditions Units min max min typ max min max VPP = 40V, ISIG = 5mA 30 26 38 48 VNN = -160V ISIG = 200mA 25 22 27 32 VPP = 100V, 25 22 27 33 ISIG = 5mA Small Signal Switch On-resistance RONS VNN = -100V ISIG = 200mA 18 18 24 27 ISIG = 5mA 23 20 25 30 VPP = 160V, VNN = -40V ISIG = 200mA 22 16 25 27 Small Signal Switch ISW = 5mA, VPP = 100V, RONS 20 5 20 20 % On-resistance Matching VNN = -100V Large Signal Switch On-resistance RONL VSIG = VPP - 10V, ISIG = 0.8A 15 VSIG = VPP - 10V and VNN + 10V 5 0.4 10 15 A Switch Off Leakage Per Switch ISOL DC Offset Switch Off RL = 100K 100 0 100 100 mV DC Offset Switch On RL = 100K 100 0 100 100 mV ALL SWs OFF 0.1 10 A VPP Quiescent Supply Current IPPQ ALL SWs ON ISW = 5mA ALL SWs OFF VNN Quiescent Supply Current -0.1 -10 A INNQ ALL SWs ON ISW = 5mA 0.8 A Switch Output Peak Current VSIG duty cycle 0.1% Output Switch Frequency fSW Duty Cycle = 50% 50 KHz VPP = 40V, 6.5 7 8 VNN = -160V IPP VPP Operating Supply Current 50kHz Output VPP = 100V, Switching mA 5 5.5 5.5 Frequency with VNN = -100V no load INN VNN Operating Supply Current VPP = 160V, 5 5 5.5 VNN = -40V VDD Average Supply Current IDD fCLK = 5MHz, VDD = 5V 4 4 4 mA IDDQ 10 1 10 10 A VDD Quiescent Supply Current VDD DOUT Source Capability V VOH IOUT = -400A -0.7 DOUT Sink Capability VOL IOUT = +400A 0.7 V 10 10 10 pF Logic Input Capacitance CIN Logic Input High VIH 4.75V < VDD < 5.25V 2 2 2 V Logic Input Low VIL 4.75V < VDD < 5.25V 0.8 0.8 0.8 V
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CPC7220
Electrical Characteristcs
AC Characteristics (over recommended operating conditions unless otherwise noted) 0C Parameter Symbol Test Conditions min max 150 Set Up Time before LE rises tSD Time Width of LE tWLE 150 150 Clock Delay time to Data Out tDO Time Width of CL tWCL 150 Set Up Time Data to Clock tSU 15 Hold Time Data from Clock tH 35 50% duty cycle fDATA = fCLK/2 5 Clock Freq fCLK Clock Rise and Fall Times tr, tf 50 Turn On Time tON VSIG = VPP -10V, RL = 10K 5 Turn Off Time tOFF VPP = 160V, VNN = -40V 20 Maximum VSIG Slew Rate dv/dt VPP = 100V, VNN = -100V VPP = 40V, VNN = -160V f = 5MHz, 1K/15pF load -30 Off Isolation KO f = 5MHz, 50 load -58 Switch Crosstalk KCR f = 5MHz, 50 load -60 Output Switch Isolation IID 300ns Pulse Width, 2.0% Duty Cycle 300 Diode Current Off Capacitance SW to GND CSG(OFF) 0V, 1MHz 5 17 On Capacitance SW to GND CSG(ON) 0V, 1MHz 25 40 +VSPK VPP = 40V, VNN = -160V, RL = 50 -VSPK +VSPK VPP = 100V, VNN = -100V, RL = 50 Output Voltage Spike -VSPK +VSPK VPP = 160V, VNN = -40V, RL = 50 -VSPK Charge Injection Q VPP = 100V, VNN = -100V, VSIG = 0V +25C +70C Units min typ max min max 150 150 ns 150 150 ns 150 150 ns 150 150 ns 15 8 20 ns 35 35 ns 5 5 MHz 50 50 ns 5 5 s
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20 300 5 20 21 30 25 40 -30 -58 -60 -33 150 880 -
20 300
V/ns
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-30 -58 -60
dB dB mA pF pF
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5 25
20 50
-
mV
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pC
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CPC7220
Logic Timing Waveforms
DN-1 DIN
50%
DN
50%
DN+1
LE
50%
50%
tWLE tSD CLK tSU DOUT tOFF
50%
50%
tDO
tH
50%
IN
90% 50%
VOUT OFF
(TYP)
ON
CL
tWCL
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50%
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tON
10%
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CPC7220
CPC7220 Description
The CPC7220 takes a serial stream of input data along with a synchronous clock signal. As the clock transits from low to high, the data at the input of each shift register is shifted through from SR(n) to SR(n+1). A high data bit, a "1," represents an ON switch; a low data bit, a "0," represents an OFF switch. Data is input and shifted through the internal shift register until all eight shift register positions, SR0 through SR7, are in the desired state. DIN: The data-in line presents data bits to the CPC7220 to be shifted through the internal shift register. CLK: The clock signal's rising edge is associated only with shifting data into and through the shift register. CL: The clear line overrides all other inputs. When CL is high, the shift register is cleared to all 0s and all latches are set low, which causes all output switches to be turned OFF immediately. When CL is low, all output switches remain in whatever state they are in, ON or OFF, in response to CLK, latch inputs, and the LE signal. turns a switch ON. Two or more CPC7220 devices can be cascaded to form an n-switch arrangement. The DOUT pin of the first is connected to the DIN pin of the next in the series. All devices are connected to the same clock (CLK) signal. LE of all devices would normally be connected, as would CL, but this is not necessary. The first data bit applied to DIN of the CPC7220, whether it's a single device or several cascaded devices, ripples through to the last switch output in line after the application of a full clocking sequence of 8 clock pulses per CPC7220. Setting the serial I/O device to output the most significant bit (MSB) first, results in the MSB appearing on SW7 of the last device in line after a full clocking sequence.
IN
DIN CLK CL LE
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DIN CLK CPC7220 CL LE DOUT DIN CLK CPC7220 CL LE DOUT DIN CLK CPC7220 CL LE DOUT
SW0
PR EL
LE: latch enable controls the state of the latches and thus the state of the eight switches. If LE is high, then the latches do not change states, but retain their most recent status: either ON or OFF. With LE high, input data and CLK have no effect on the state of the output switches. If LE is low, then all latch outputs and their switch states follow the inputs from the shift register. LE is overridden by CL: no matter what state LE is in, CL clears the latches. See table on page 10. DOUT: The data-out pin is the output of SR7. After eight clock pulses, the first bit of eight input data bits is shifted to SR7 and appears on DOUT. SW0 - SW7: The CPC7220 provides eight highvoltage SPST output switches with a typical onresistance of 20. The two connections of each switch are not polarity-sensitive. VPP and VNN: Voltage inputs to the level shifters for each switch channel that translate the voltage level of the latch output signals to an appropriate level for the voltages being switched. The high-voltage output switches are turned on and off in response to the data sent into the latches from the shift register: data 0 turns a switch OFF, data 1 8
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SW7
SW0
SW7
SW0
SW7
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Truth Table
D0 L H L H L H L H L H L H L H L H X X D1 D2 D3 D4 D5 D6 D7 LE L L L L L L L L L L L L L L L L H X CL L L L L L L L L L L L L L L L L L H SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 OFF ON OFF ON OFF ON
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OFF ON OFF ON OFF ON OFF ON HOLD PREVIOUS STATE OFF OFF OFF OFF OFF OFF OFF OFF
OFF ON
X X
Notes:
X X
X X
X X
X X
X X
X X
1. The eight switches operate independently.
2. Serial data is clocked in on the L H transition CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs.
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CPC7220
Manufacturing Information Soldering For proper assembly, the component must be processed in accordance with the current revision of IPC/JEDEC standard J-STD-020. Failure to follow the recommended guidelines may cause permanent damage to the device resulting in impaired performance and/or a reduced lifetime expectancy. Washing Clare does not recommend ultrasonic cleaning or the use of chlorinated solvents.
Pb
RoHS
2002/95/EC
e3
28-Pin PLCC Package
12.319/12.573 (0.485/0.495) 11.430/11.582 (0.450/0.456) 0.020 MIN (0.004 MIN)
Recommended PCB Land Pattern
A
0.660/0.813 (0.026/0.032)
RY
10.90 (0.429) 1.27 (0.050)
MECHANICAL DIMENSIONS
0.65 (0.026)
12.319/12.573 (0.485/0.495)
11.430/11.582 (0.4500.456)
IN
0.330/0.533 (0.013/0.021) 2.286/3.048 (0.090/0.120) 4.191/4.572 (0.165/0.180)
Pin 1
10.90 (0.429)
2.40 (0.094)
1.27 TYP (0.050 TYP)
PR EL
9.00 0.20 (0.354 0.008) 7.00 0.10 (0.276 0.004) 7.00 0.10 (0.276 0.004) 9.00 0.20 (0.354 0.008) 0.22 0.05 (0.009 0.002)
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1.40 0.05 (0.055 0.002) 0.60, +0.15/-0.10 (0.024, +0.006/-0.004)
Dimensions mm(Max)/mm(Min) (inches(Max/inches(Min))
48-Pin LQFP Package
Recommended PCB Land Pattern
8.50 (0.335)
1.60 Max (0.063Max)
0.50 (0.020) 8.50 (0.335)
Pin 48 Pin 1
0.05 Min / 0.15 Max (0.002 Min - 0.006 Max)
0.50 (0.020)
0.30 (0.012)
1.45 (0.057) Dimensions mm (inches)
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CPC7220
For additional information please visit our website at: www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7220-R00H (c)Copyright 2009, Clare, Inc. All rights reserved. Printed in USA. 4/20/09
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